1. Field of the Invention
The present invention pertains in general to a non-volatile memory cell structure and method of manufacturing the same, and more particularly, to a split-gate non-volatile memory cell and method of multilevel self-convergent programming of the non-volatile memory cell.
2. Description of the Related Art
In a conventional split gate flash memory or Electrically Erasable Programmable Read-Only-Memory (“EEPROM”), commonly known as a non-volatile memory, programming may be achieved by storing electrons in the floating gate of the memory cell. Under certain bias conditions, electrons in a semiconductor substrate can tunnel through a thin oxide layer disposed between the floating gate and the semiconductor substrate to allow for charge storage in the floating gate. The tunneling electrons may be created by a conventional hot-electron injection scheme or a Fowler-Nordheim tunneling scheme.
In a conventional hot electron injection scheme, a high voltage is applied to the control gate (word line) of a memory cell, and a low or zero voltage is applied to the drain (bit line). When electrons in a channel region disposed between the source and drain regions of the cell attain an energy level higher than the barrier potential of the thin oxide layer disposed between the channel and floating gate, some of the electrons will tunnel through the thin oxide layer and inject into the floating gate. However, not all electrons in the channel region will attain an energy sufficient to tunnel through the thin oxide layer. The probability that an electron will tunnel through the thin oxide layer is proportional to the voltage difference between the control gate and drain region.
In addition, the number of electron charges proportional to the voltage difference between the control gate and drain will appear on the floating gate. These charges impose an electric field on the channel region beneath the floating gate. This electric field is known as the threshold voltage. The threshold voltage determines whether a memory cell is “storing” any data or value. For example, a logic value of “0” may be represented by setting a high threshold voltage and a logic value of “1” may be represented by a low threshold voltage.
FIG. 1 shows a cross-sectional view of a conventional split gate flash memory cell 10. Memory cell 10 includes a p-well 12, a source 14, a drain 16, a floating gate 18 and a control gate 20. Drain 16 also includes a lightly-doped n-region 16-1 and a heavier-doped n-region 16-2 to form an N/N+ drain. Drain 16 is connected to a bit line (BL), source 14 is connected to a source line (SL), and control gate 20 is connected to a word line (WL). In general, different threshold voltages of memory cell 10 may be created by providing a fixed voltage to control gate 20 and modulating the voltage provided to drain 16.
Memory cell 10 may be erased with the Fowler-Nordheim tunneling scheme. Under this scheme, a high voltage, e.g., 14 volts, is provided to control gate 20, and 0 (zero) volt is provided to drain 16, source 14 and p-well 12. Under these conditions, electrons stored in floating gate 18, composed of polysilicon material, tunnel through a dielectric layer 22 to control gate 20, also composed of polysilicon material. Therefore, the Fowler-Nordheim tunneling scheme is also known as “poly-to-poly tunneling” scheme. During read operations, approximately 3 volts are provided to control gate 20, 2 volts are provided to drain 16, and source 14 and p-well 12 are grounded. To achieve source-side hot electron injection scheme for programming, a threshold voltage, e.g., 1 volt, is provided to control gate 20, a high voltage, e.g., 11 volts, is provided to drain 16, and source 14 and p-well 12 are grounded.
To determine whether a memory cell has been programmed to the desired value, the conventional flash memory cell may be programmed for a predetermined time period. The value of the memory cell is then verified, and the memory cell may be repeatedly programmed until the desired value has been reached. This is an iterative process. Alternatively, a small voltage may be applied to bit line BL to verify the potential on the floating gate. This process continues until the potential on the floating gate has reached the desired value. Regardless of what method is used, the conventional programming techniques are time-consuming and difficult to control due to repeated programming and verification of the memory cell.
Furthermore, the conventional split gate flash memory cell only performs a one-bit programming operation, e.g., “0” or “1”. However, due to an increased demand for a large memory programming capacity together with a rapid data-reading capability, it is desirable that the memory cell performs multilevel programming operations and be able to rapidly read the stored data.